On-chip debug interface exposes protected memory or control
A production debug/test interface permits a protected capability beyond the documented physical-access authorization.
Candidate CWE: CWE-1191
Test hypothesis#
Use documented read-only diagnostics on an owned suitable unit to compare expected locked state with actual access to a synthetic protected region. Avoid unlock, erase and fuse operations.
Evidence required#
Chip/board version, lifecycle configuration, physical-access model, requested region and demonstrated unauthorized read or control.
Rule out false positives#
Visible JTAG pads, an accessible device ID or a development lifecycle state alone do not demonstrate protected-data access.
Playbook and command references#
- Hardware interfaces: production debug access and protected data — Distinguish diagnostic output from privileged UART, JTAG/SWD and firmware-secret boundary failures on an owned lab unit.
Find the associated command snippets
Referenced by these target playbooks#
Report checklist#
- Capture the affected version, configuration, identities, and object ownership.
- Preserve a valid baseline and a negative control.
- Reproduce the forbidden data access, action, or state change on controlled fixtures.
- Explain the intended security rule and why the observed behavior violates it.
- State prerequisites, uncertainty, cleanup, and the smallest demonstrated impact.
Conditional ATT&CK mapping#
No direct ATT&CK mapping selected. Record the weakness and demonstrated impact without forcing an adversary-behavior classification. See the mapping guide.